The demand for smaller, higher performance semiconductor dice which support portable communications devices, including memory cards, smart cards, cellular telephones, and portable computing and gaming devices, has motivated the development of new techniques for producing smaller and thinner semiconductor devices.
Flip-chip packaging technology has found widespread use because of its advantage in size, performance, flexibility, reliability and cost over other packaging methods. Flip chip packaging employs direct electrical connection of face-down integrated circuit (IC) chips onto substrates, circuit boards, or carriers, by means of conductive bumps on the chip bond pads, replacing older wire bonding technology where face-up chips sit on substrates with wire connection to each bond pad.
Many of the flip-chip bumping techniques developed in recent years have focused on realizing bumps or solderable metallizations directly on the peripheral bond pads of a semiconductor chip. Solder bumping by screen printing solder paste can be used for chip I/O pitches down to 200 micron. However, with increasing IC complexity, the IC pin count has also increased drastically, so that if only peripheral pads were used, pitches that are less than 60 micron would be necessary. Therefore, in order to package these IC chips using flip-chip technology, the peripheral I/O pads are usually redistributed into area array pads with larger pads and a relaxed pitch. Such redistribution is typically accomplished by physically connecting the peripheral pads to the area array pads using conducting leads formed on the semiconductor chip.
Redistribution of I/O pads for flip chip packaging typically involves several process steps such as: bumping of peripheral bond pads; spinning of dielectric layer; photo imaging for opening of bond pads; formation of seed layer; full area metal deposition; photo masking for defining the redistribution lines; metal etching; spinning of solder masks and photo imaging for opening of redistributed pads; bumping of redistributed pads; and solder stencil printing.
During flip chip packaging, the IC chip with bump array can be placed facedown on a substrate with a matching bump array, and the assembly is heated to make a solder connection. The solder bumps in the matching bump array on the substrate are routed to a ball grid array (BGA) attached to the substrate via connection lines in the substrate. With the increasing density of the bump array, customized substrates with multilayered routing are typically used for today's flip chip ICs in order to fan-out all traces of the connection lines.
The bump arrays are placed on matching bump pads on a top side of the substrate. The matching bump pads are then connected to substrate BGA pads for attaching the BGA on a bottom side of the substrate via six layers of routing lines and vias that couple between these layers. The substrate unit cost increases drastically due to the additional layer count and advanced design rules to lay out the substrate routing lines. Therefore, there is a need to reduce substrate unit cost by using standard or semi-standard substrates with fewer routing layers and less stringent design rules.
As is well known in the field of integrated circuit packaging, flip-chip mounting provides smaller footprint and lower manufacturing cost. However, processing methods and materials can prevent further improvements in size and numbers of bump pads and routing lines. Further, additional routing layers and vias adversely affect electrical integrity and performance. To date, integrated circuit packages have not successfully addressed manufacturing, yield and performance issues. A new approach must be found in order to increase the manufacturing and performance of integrated circuit packages.
Thus, a need still remains for an integrated circuit package system to improve routing lines and vias while maintaining electrical integrity and performance. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to save costs, improve efficiencies and performance, and meet competitive pressures, adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.